FIG. 1 of the accompanying drawings shows a typical active matrix display. Such a display is made up of a matrix 2 of picture elements (pixels), arranged in M rows and N columns. Each row and column is connected to an electrode, with the column electrodes being connected to the N outputs of a data driver 4 and the row electrodes being connected to the M outputs of a scan driver 6.
The pixels are addressed one row at a time. The scan driver includes an M-phase clock generator, which produces a series of clock pulses as shown in FIG. 2 of the accompanying drawings. Each clock pulse OUTi controls the activation of row i for each i such that 1≦i≦M. It is usual for the pulses to be non-overlapping, such that no two pulses are high at the same time.
All the pixels of one row may be addressed simultaneously, or they may be addressed in B blocks of b pixels, where bB=N. In the latter case, the data driver may also include a B-phase clock generator of the type described, such that each clock pulse OUTi activates block i for each Ii such that 1≦i≦B.
Normal operation of the display is such that data is sampled onto the pixels from top to bottom and from left to right, corresponding to the timing shown in FIG. 2. However, it is a common requirement for the direction of sampling to be switchable, such that data is sampled onto the pixels from bottom to top and/or from right to left. In this way, it is possible to reflect or rotate the image displayed without re-ordering the input data. Such re-ordering requires considerable additional circuitry, such as additional memory sufficient to store the whole image.
In this case, the clock generators must in addition be able to operate bi-directionally, producing either clock pulses as in FIG. 2, or clock pulses of the type shown in FIG. 3 of the accompanying drawings. Each pulse OUTi in FIG. 3 (for each i such that 1≦i≦M) still activates row i. However, pulse OUTi occurs before pulse OUTi-1, whereas in FIG. 2 pulse OUTi occurred after pulse OUTi-1.
Scan drivers of the type described may be formed directly on the display substrate, reducing the number of connections required to the display. This is advantageous, since it reduces the area occupied by the connector, and leads to a display which is more mechanically robust. In such cases, it is common to use a single type of transistor for the clock generator circuit. For example, the circuit may be composed of only n-type transistors, rather than a mixture of n- and p-type transistors, as commonly used in CMOS circuits. The use of a single type of transistor is advantageous for manufacturing cost. However, it is difficult to design low-power, high-speed logic, such as AND gates and inverters, using a single type of transistor.
A clock generator for use in a scan driver may be formed from a shift register. A shift register is a multi-stage circuit capable of sequentially shifting a sequence of data from stage to stage along its length in response to a clock signal. In general, a shift register may shift an arbitrary sequence of data. However, when a shift register is used as a clock generator in a scan or data driver, it is only required to shift a single high state along its length. Such a shift register is referred to as a “walking one” shift register, and may or may not be capable of shifting an arbitrary sequence of data.
An example of such a type of clock generator is disclosed in U.S. Pat. No. 6,377,099, and is shown in FIG. 4 of the accompanying drawings. Each stage is composed of a reset-set (RS) latch 24, with an additional gate 26 to control the passage of the clock, such that the clock is passed to the output of the stage when the RS latch is set, and the output is pulled to an inactive state when the RS latch is reset. The output of the gate is connected to the set input of the next stage, and to the reset input of the previous stage. The output of the gate also forms an output of the scan driver.
In addition, U.S. Pat. No. 6,724,361 describes a similar clock generator which uses non-overlapping clocks.
A RS latch is a well-known logic block. As shown in FIG. 4, it has a set input, S, and a reset input, R, and two outputs Q and QB, where QB is the logical complement of Q. It operates according to the following truth table 1:
TABLE 1RSQn00Qn-101110011Xwhere 0 and 1 are the low and high logic levels respectively, X is an undefined or disallowed state, Qn is the current output state, and Qn-1 is the previous output state.
A typical implementation of a RS latch is shown in FIG. 5 of the accompanying drawings, and is composed of two cross-coupled NOR gates, 8 and 10. When the set input, S, is raised to a logic high state, the output of NOR gate 8 falls to a low state, irrespective of the state of its other input. If the reset input, R, is at a low level (as required by the truth table), the output of NOR gate 10 rises to a high level. Thus Q and QB attain the required states.
When the set input is subsequently lowered to a logic low state, and while the reset input remains in a logic low state, the high state on Q causes NOR gate 8 to output a low state, which in turn causes NOR gate 10 to output a high state. The Q and QB inputs therefore retain their previous values.
This state illustrates the bi-stable nature of the flip-flop: there is a positive feedback loop from the Q output, via NOR gate 8, the QB output, and NOR gate 10, back to the Q output. If the Q output is affected by noise, its value will be restored by NOR gate 10 and the state of QB; similarly, QB is held by NOR gate 8 and the state of Q. The state of the flip-flop's outputs is therefore immune to the effects of noise (at least within reasonable limits).
FIG. 6 of the accompanying drawings shows the simplest implementation of a RS latch in a single-channel process, and is similar in operation to circuits described in U.S. Pat. Nos. 6,778,627, 5,434,899 and 5,949,398. Two transistors, 12 and 14, connect the Q output to a high- or low-level supply when the S or R inputs are high respectively. When S and R are both low, both transistors are off, and the state of the flip-flop is preserved by the trapped charge on the capacitance of the Q node. This capacitance may be explicit or parasitic. An additional circuit is needed to generate a QB output: this would be as in FIG. 6 of the accompanying drawings, but with the S and R inputs reversed.
Transistor 12 may also be diode-connected, such that the connection to Vdd is replaced by an additional connection to the S input, without affecting the operation described above.
A major disadvantage of this architecture is that there is no positive feedback, and the Q node is floating. Thus any noise in the system can easily be coupled onto the node, and its state may be corrupted. The state will not be restored unless either the R or S input is raised to a high level.
An additional disadvantage is that the Q node is not fully charged to Vdd in the set state. An n-channel transistor conducts when its gate is higher than the source by at least the threshold voltage of the transistor, VTH. Therefore, if the S input is raised to Vdd, transistor 12 will only conduct until Q reaches (Vdd−VTH). In many applications, it is desirable for the level of the Q and QB outputs to swing from the high to the low voltage supply rails.
FIG. 7 of the accompanying drawings shows a second implementation of a RS latch in a single-channel process, and is similar in operation to circuits described in U.S. Pat. Nos. 7,038,653, 6,922,217, 6,845,140.
To effect a reset operation, the R input is raised to a high level, discharging the Q output through transistor 20, and turning off transistor 25. Transistor 18 is diode-connected, so conducts if its source is at least one threshold drop below the high voltage supply, Vdd. QB is therefore raised to a high level by transistor 18, turning on transistor 22. Thus, when the R input is subsequently lowered to a low state, transistor 22 maintains the low state on Q, and transistor 18 maintains the high state on QB. The circuit therefore shows good noise immunity in the reset state.
To effect a set operation, the S input is raised to a high level, charging the Q output to a high level through transistor 16. This turns on transistor 25, discharging the QB output, which in turn turns off transistor 22. However, when the S input is subsequently lowered to a low state, transistors 16, and 22 are all off, and the Q node floats. The circuit therefore has poor noise immunity in the set state. In addition, Q is not fully charged to Vdd, for reasons described previously.
A further disadvantage of the circuit of FIG. 7 of the accompanying drawings is that, in the set state, transistors 18 and 25 are both on, and a short-circuit current flows from the high to the low power supply. In a low-frequency circuit, such as the scan driver for an active matrix display, this short-circuit current can be significant, perhaps increasing the power consumption of the circuit by a factor of 2 to 4.
Other approaches to this circuit, such as described in U.S. Pat. Nos. 6,690,347, 5,701,136, 5,410,583, 5,222,082, 6,813,332 and 6,928,135, all exhibit at least one of the two disadvantages described: there is a floating node or a short-circuit current in at least one state of the latch.
U.S. Pat. No. 7,038,653 also describes a single-channel output switch for a shift register stage, and illustrates the use of a bootstrap capacitor, as shown in FIG. 8 of the accompanying drawings. The Q and QB inputs are connected to the Q and QB outputs of a latch respectively, and the CK input is connected to a shift register clock. The Q output may not reach the high supply rail, and therefore not fully conduct the voltage of the clock to the OUT pin. The bootstrap capacitor, 61, acts to increase the gate voltage of transistor 27 when CK rises. Its operation is as follows: the gate of transistor 27 is raised by the logic to a point where it conducts; when the clock rises, the rise is conducted to the output; this rise is coupled to the gate of transistor 27 by the capacitor 61, increasing the gate voltage, and ensuring that transistor 27 continues to conduct until its source and drain voltages are substantially equal. Transistor 29 holds the output at the low supply voltage, Vss, when the QB input is high: no bootstrap is necessary, since an n-channel transistor will conduct Vss as long as its gate is held at least (Vss+VTH): QB is typically at a higher voltage.
A second type of latch is the D latch. A well-known type of such a latch is shown in FIG. 9 of the accompanying drawings. When CK is high, the input, D, is copied to the output Q, and its logical complement to the complementary output QB. When the clock falls, the state of Q is held. A positive feedback loop is formed by the switch 31, and the value of D is latched.
US patent application publication number 2007/0091014 describes a single-channel shift register made from a cascade of D latches. FIG. 10 of the accompanying drawings shows the latch circuit described. When CK is high (and its complement, CKX is low) the latch is transparent, and the output OUT follows the input IN. When CK is low, the input data is latched and held on the output.
The circuit has similar disadvantages to those previously described: transistors 28 and 30 are always on, and one of transistors 32 and 34 is on for any data. Therefore a short-circuit current flows from Vcc 1 to the low supply rail Vss, increasing the power consumed by the circuit. In addition, the output voltage is lower than Vcc1, except in the case where Vcc2 is at least equal to (Vcc1+VTH). However, generating a higher-voltage Vcc2 increases both the power consumption of the circuit and the complexity of a reference-generation circuit.